The ASICCLK generates the variable CPU and system clocks as well as a fixed VIA clock of 9 MHz out of an external clock of 18 MHz. The VIA clock was fixed at 9 MHz to give the internal timers a well defined time base. Besides the main clock generator the ASICCLK builds select signals for the other parts of the circuit and contains a clock generator for the watchdog.
Clock Generator
The clock generator internally works fully synchronous. Initially the external clock should be 24 MHz and thus allow a maximum CPU frequency of 12 MHz. But first tests showed, that especially in virtual memory mode of the ASICMMU the added delays of the ASICMMU, the VSRAM and the RAM grew to much, in spite of the usage of RAM with 10 nS access time. The total delay was too large for a stable operation at 12 MHz. So I reduced the maximum CPU clock to 9 MHz.
When accessing i/o areas or the EPROM, the CPU is clocked down in dependence of the maximum speed of the respective device up to about 1 MHz. Accesses to the VRAM are synchronized through the RAMFREE signal of the ASICCRT. After reception of a DMA request the CPU clock is stopped for 1 clock after completion of the current clock cycle and only the system and VIA clocks are generated at 9 MHz further on. Besides this the DMA acknowledge signal is asserted, the bus control is taken by the ASICIDE and the CPU is separated from the bus. In addition a keyboard scan clock is generated, which is used by the ASICETC for a safe detection of clock changes at the keyboard interface.
Watchdog Clock Generator
After a reset the watchdog clock generator automatically generates a clock for the watchdog timer, which is part of the reset component MAX1232. If one doesn’t need a watchdog function in a system, he can leave the system in this state. But if you want, a simple access to memory bank $F9 is sufficient. This turns off the automatical clock generation for the watchdog and from now on the software must access bank $F9 about every 1.2 seconds.Missing to do this leads to a reset by the MAX1232. This function can detect system hang-ups and allows a defined system restart.
Generation of Select Signals
As the ASICCLK has only relatively few connections, which the part can utilize, the multiplexed bank addresses A[16..23] at the data bus are used for the generation of the select signals. For that reason the single components need plenty of room in the address space of the CPU. But this is at 16 MB large enough so I got no problems with the generous usage of addresses.
Memory Usage of the PC65816 V2