My design uses 5V Lattice devices. These were easy to obtain, when I began to work with CPLDs and are it still today. Another advantage was, that I could insert most CPLDs into a socket, what simplified the construction and testing. The ispLSI1032-70LJ have got a heat sink to keep cooler.

The JEDEC files, which where generated by the Lattice development software, can be sent through a download cable and the software ispVM directly into the circuit. Because I used two different device families (M4A5 and ispLSI), the circuit has got an ISP and a JTAG interface. The single devices are chained together for programming. The JTAG chain consists in of ASICCLK and ASICMMU, the ISP chain of ASICCRT, ASICIDE1, ASICIDE2 and ASICETC.

The following CPLDs are used: