Overview

The ASICMMU contains besides the virtual memory controller circuits to guarantee system integrity. The operating mode can be choosen by the contents of 2 registers, which can be read and dependent on some conditions also changed by the CPU. The ASID register contains in virtual memory mode the current active address space id. Through the control register the functions of the ASICMMU can activated.

Why virtual Addressing ?

You may ask, why I implemented the possibility of virtual addressing for the PC65816 V2. But if you consider, that this computer is provided with 4 MB main storage which is rather much for 65XX single board systems and the system is designed for multitasking operation, you run into 2 main problems, when using direct addressing of RAM. The memory areas of different tasks should possibly be separated, so that an error in one task will not damage the memory contents of other tasks on the computer. In addition in multitasking operation there is the problem of memory fragmentation caused by multiple memory reservations and releases. These problems can be avoided by using virtual addressing.

Operation of virtual Addressing

The memory is divided into 128 segments of 32 kB each. The CPU’s upper address lines are not directly connected with the address lines of the memory, but with the address lines of a special RAM (VSRAM). The VSRAM’s data lines are used for addressing the main RAM. The contents of the VSRAM is thus very important for the calculation of the effective memory addresses. The upper used address lines of the VSRAM are driven by the contents of the ASID register. Per 32 kB virtual segment 1 byte in VSRAM is used. The virtual address space can be up to 4 MB. So every address space uses 128 Bytes of the VSRAM. For 128 possible address spaces there is a maximum of 16.384 bytes of the VSRAM in use. In the calculation for the real memory addresses the RAM address lines A22 and A23 are fixed to 0, because the RAM is located in the lower 4 MB of the real address space. The RAM address lines A15-A21 are driven by the data lines D0-D6 of the VSRAM. D7 of the VSRAM has a special meaning. If this bit is 1, then this virtual 32 kB segment is read only. The memory controller physically prevents writes to that segment and is able to assert the ABORT signal, if this function is activated in the control register. Through the control register another security function can be activated, which prevents an opcode fetch from a read / write segment and generates an ABORT, too. The real segment 0 ($000000-$007FFF) is reserved for read/write access of the operating system. So the value $80 isn’t a legal value in any VSRAM byte. Thus this value is used to flag an invalid memory segment in the table. Any try to access such a segment ends in an ABORT. An access to addresses beyond 4 MB in user mode (a description follows in the next section) leads to an ABORT. It is the task of the operating system to manage the VSRAM tables and link the ABORT vector with a suitable processing routine. After a reset the virtual memory mode is at first not active. This allows the systems software to build up the necessary tables in the VSRAM. During DMA accesses the addressing is always real, because these don’t run in a defined program context, but parallel and independent. Thus the contents of the ASID register at this time is not foreseeable.

System- and User Mode

Through the control register the system can be switched from system to user mode. In this mode there are some limitations for the programs. The access to addresses beyond 4 MB is no longer possible and leads to an ABORT. Because all addresses of control registers and i/o devices are beyond this line, there is no possibility for a program in user mode to directly access these units. Even a switch back into system mode is impossible in this operation mode. The only way back from user to system mode is a soft- or hardware interrupt. In this case the CPU fetches the appropriate jump vector from the memory and this processing enables the way back to system mode using the vector pull line of the processor. So there is an exactly defined interface between application programs and the operating system.

Further Safety Mechanisms

Beside changing memory of other tasks a program could harm the systems stability by using several instructions. For this reason the instructions SEI, STP, WAI and XCE can be intercepted in user mode. At the data bus the opcode NOP is inserted instead and a NMI interrupt generated.

MMU Registers

The ASID register is accessible at $F88000 and uses bits 0-6 for the presentation of a maximum of 128 address spaces. The CPU can read and write the ASID register.

The control register is located at $F88001. It’s structure can be found in the following table:

The VSRAM starts at $F80000. It supports read and write accesses and the tables have the following structure:

The equivalent schematicof the ASICMMU can be downloaded here.