The core circuit consists of the CPU 65816, a reset controller, a clock generator (ASICCLK), SRAMs (up to 8 x 512k), an EPROM 27512 and a memory controller (ASICMMU).
The ASICCLK generates a variable CPU- and system clock using an external 18 MHz clock. The maximum CPU frequency while accessing RAM is 9 MHz. When accessing EPROM or the i/o devices, the clock is synchronically reduced. During DMA operations CPU clock is completely stopped and only the system clock generated. The ASICCLK synchronizes accesses to the CRT RAM in company with the CRT controller as well. This prevents screen interferences on r/w operations to the VRAM. The ASICCLK also generates various address select signals and allows together with the reset controller a watchdog function.
The memory controller is configurable via software. The necessary tables for the management of the virtual storage are placed in a special VSRAM (512k). The single virtual storage segments have a size of 32kB each. After a reset the system first is in real memory mode and the EPROM is active. After copying the EPROM content into the SRAM, the EPROM can be switched off via software. When the virtual storage tables are built up in the VSRAM, the system can be switched into virtual memory mode.
To safeguard the operating system the system supports a system- and a user mode. The switching from system- to user mode can be done by software. The change back into system mode is solely performed by a hard- or software interrupt and so through an exactly defined interface. In the user mode a program can only access the RAM (addresses up to 03FFFF). Accesses beyond this limit lead to an ABORT interrupt. Accesses to invalid storage segments or write accesses to read-only segments result in an ABORT interrupt, too. Optionally a program execution from a read-write segment can lead to an ABORT, to prevent code execution from a data segment. Because some opcodes can be potentially dangerous for system integrity, they can be suppressed in user mode, too. As soon as the opcodes SEI, STP, WAI or XCE appear on the data bus, they will optionally be replaces by a NOP and a NMI interrupt is generated.
The screen signal is built by the ASICCRT in conjunction with a data buffer, the VRAM (64k) and the character generator (2732). First I planned to implement a switchable graphical mode. But this must be omitted because of a lack of resources in the used CPLD. Instead of this the most significant bit of a character optionally can be used for a highlighted presentation.
The IDE interface (ASICIDE1 and ASICIDE2) can drive a normal harddisc or through an adapter a compact flash card. The CPU has direct access to the IDE registers of the device as well as the internal registers of the CPLDs. The data transmission between the drive an the RAM is performed via direct memory access. To do this, the CPU is stopped for one clock for each byte to be transmitted. At the end of the operation the controller generates an IRQ.
The ASICETC contains besides the interrupt controller, a system control register, an interface for the real time clock RTC58321 and an EEROM emulator a bidirectional PS/2 keyboard interface. The EEROM emulator replaces a 9346 EEROM for the configuration of the ethernet controller, because some parameters can be set only this way at the startup phase, especially the full duplex bit. The keyboard interface works without any CPU intervention and generates for every received scancode an IRQ. The CPU can use the controller to send commands to the keyboard, which the controller transmits to the keyboard independently.
An accu of 3.6 V supplies the real time clock RTC58321 if the system is without power. May be that the clock will become obsolete in a later development step, because the time could be requested via NTP across the network
For the ethernet controller I use a RTL8019AS. The RJ45-Connector contains already the necessary ethernet transformators and the LEDs. The controller allows 10 MBit speed and it can generate IRQs, too.
Last, not least the circuit contains a VIA 6522. This part includes besides versatile interfaces 2 programmable timers. The 6522 can generate IRQs.
The schematic can be downloaded under this link: